Insulating spacers are widely used in the process of manufacturing integrated circuits. These spacers are mainly used for two important applications namely to isolate two conductive patterns on from another and as masking elements. Especially if their sole function is their use as masking elements, sacrificial spacers are often used, i.e. they are removed later on in the process. However, for quite a number of applications structural spacers are used because both their function as insulating elements as well as masking element is required. Examples of such structural spacers can be found, e.g. in a MOSFET, particularly in a MOSFET with a lightly doped drain (LDD) and/or source, where the spacers are located at the sidewalls of the polysilicon gate and are used to isolate the gate from the drain/source as well as to serve as a masking elements for the implantation of the lightly doped drain/source regions. Another example of such structural spacers can be found, e.g. in a bipolar device, particularly in the emitter-base region as e.g. in FIG. 1 of the U.S. Pat. No. 5,439,833, where the spacers are used to define the emitter opening as well as to isolate the conductive layer connecting the emitter from the base connection (the base polysilicon).
Especially in the two aforementioned examples, the formation of the (structural) spacers is a very critical part of the manufacturing process because this spacer formation has a large influence on the definition of the intrinsic device and therefore on the device characteristics. Because the dimensions of the intrinsic device are very small, i.e. typically in the deep sub-micron range, one has to be able to define these spacers in a very controllable and reproducible way in order to be able to meet the stringent yield and reliability specifications. This problem will even be more stringent in the future due to the ongoing downscaling of the device dimensions.
In view of this problem a spacer formation process should comprise a minimum of process steps in order to reduce yield problems, should be simple to reduce process complexity and increase yield and reproducibility. Furthermore wafer handling, exposure to a possible contaminating ambient and exposure to an oxidizing ambient has to be avoided as much as possible because this might necessitate the introduction of extra process steps, particularly cleaning steps and extra etching steps, and therefore has a negative influence on yield, reliability and cost.